Semiconductor Wiki Project
If you have not already, please join SemiWiki.com as my guest. If you put “iPad2″ as the referrer you may win one!
SemiWiki is a growing online community of professionals involved with the semiconductor design and manufacturing ecosystem.
I hope to see you there!
D.AN.
Silicon Valley Blog 2010 in Review
Future blog posts will be on SemiWiki.com, I hope to see you there!
The stats helper monkeys at WordPress.com mulled over how this blog did in 2010, and here’s a high level summary of its overall blog health:
The Blog-Health-o-Meter™ reads Wow.
Crunchy numbers
The Louvre Museum has 8.5 million visitors per year. This blog was viewed about 160,000 times in 2010. If it were an exhibit at The Louvre Museum, it would take 6 days for that many people to see it.
In 2010, there were 52 new posts, growing the total archive of this blog to 113 posts. There were 530 pictures uploaded, taking up a total of 43mb. That’s about 1 picture per day.
The busiest day of the year was December 13th with 1,664 views. The most popular post that day was Mentor – Cadence Merger and the Federal Trade Commission.
Where did they come from?
The top referring sites in 2010 were linkedin.com, yahoo.com, design-reuse.com, chipdesignmag.com, and Google.com.
Some visitors came searching, mostly for daniel nenni, tsmc 28nm, tsmc 40nm, dan nenni, EDA360, semiconductor yield, semiconductor design, and semiconductor forecast.
Attractions in 2010
These are the posts and pages that got the most views in 2010.
Mentor – Cadence Merger and the Federal Trade Commission December 2010
3 comments
TSMC versus Global Foundries Part II January 2010
5 comments
TSMC Yields @ 28nm! September 2010
88 comments
Mentor Acquires Magma? November 2010
29 comments
Intel versus ARM versus Synopsys July 2010
14 comments
EDA Consortium Annual CEO Forecast and Industry Vision
For those of you that have not heard, I have been asked to moderate the 2011 EDAC CEO Forecast. Having an internationally recognized industry blogger moderate this prestigious event is a significant milestone and I’m honored to be a part of it. I do need your help however, in coming up with questions for the CEO’s. Anything EDA, whatever is on your mind, let me know. EDAC has invited Social Media in to increase the transparency so let’s show them how it works! You can register here.
The EDA Consortium seeks to identify and address issues that are common to its members and the customer community that the member companies serve. By focusing on commonality and promoting cooperation, the Consortium augments the effectiveness of the tools, services and communications provided by its members.
I’m a big fan of the EDA Consortium, there is always free food and an open bar at EDAC events (I blog for food). The Kauffman Award is my favorite event since you get a full meal but the CEO panel is a close second. This year it will be Wally Rhines (Mentor), Aart de Geus (Synopsys), unfortunately Lip-Bu Tan (Cadence) is not available, Charlie Huang (Chief Strategy Officer) will step in for Lip-Bu, and representing emerging EDA companies Ravi Subramanian (Berkeley Design Automation).
Social media uses web-based technologies to turn communication into interactive dialogues.
Social Media is a group of Internet-based applications that allows the creation and exchange of user-generated content.
A common thread running through all definitions of social media is a blending of technology and social interaction for the co-creation of value.
Blogging has been an interesting experience for me. At first it was quite humbling since very few people read my blog. But once I figured it all out, I was amazed at the types of information I had access to. Since I own my domain, using analytics, I get to see where people come from and where they click to. I also get to see search engine terms and referring sites. My blogs on the foundry topics get the most views. Semiconductor IP blogs are also popular. EDA related blogs get the least amount of views, less than 1,000 people will probably read this blog out of 5,000+ subscribers. That really bothers me by the way.
As a result of my blog I also get calls and emails from financial analysts, investment bankers, venture capitols, and random strangers asking for information and opinion on the foundries and the semiconductor industry. When I bring up EDA however there is silence, the same type of silence I experienced with my first blogs. The semiconductor industry will grow 30%+ in 2010. Semiconductor IP will grow 30%+. EDA will grow 0%. That really bothers me as well. To toil 25+ years in an industry with no real growth for the foreseeable future. It’s frustrating to say the least.
So send me some questions for the EDA CEO’s. Keep in mind that the mission statement of EDAC is:
“To promote the health of the EDA industry, and to increase awareness of the crucial role EDA plays in today’s global economy”
Insanity is doing the same thing over and over again and expecting different results (Albert Einstein). Lets stop the insanity and grow this industry.
CDN LIVE 2010 Trip Report: Realizing EDA360
The question I asked in my first EDA360 blog was, “Will EDA360 be an industry transformation catalyst or a failed public relations campaign?” After various conversations with John Bruggeman and attending the CDN LIVE conference in San Jose I definitely see EDA360 as a transformational catalyst for Cadence but not necessarily for the EDA industry on a whole, yet.
CDNLive! Silicon Valley brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.
Interesting observations include:
- GDP growth world wide 5%+
- Semiconductor 32%+ 2010, 5-7% 2011
- Society is now application driven with continuous connectivity
- Apple iOS has 300k+ apps, Google Android has 100k+, Samsung has 500+
- Increased software content (60-70% engineers are now software)
- Apple, Oracle, Google now have semiconductor design capabilities
- For every $1 spent on IP it takes $3-5 to integrate/optimize/verify
- 22nm costs:
- Fab $4-7B
- Process R&D 2-3B
- Mask $5-8M
- Design costs $120-140M
Mobile OS ranking:
- Nokia
- RIM
- Android (w00t!)
- iOS
I first met John Bruggeman at the GlobalFoundries party at Disneyland. After my EDA360 blog profiling JohnB and the Unibomber I wasn’t expecting an accretive discussion. Alcohol was definitely a factor but we clicked anyway. One thing I can tell you for sure is that he is a quick study and has a great sense of humor! While I do enjoy a good gamble I would not bet against John Bruggeman on this one.
I still remember the early days of Cadence so it was nice to see they can still put on a good show! It started out with loud music and silhouette acro gymnasts acting out the different semiconductor market segments demonstrating the shift to platforms and apps, which I blogged about last week. That was one expensive multimedia extravaganza, Joe Costello would be proud!
There are already CDNLive 2010 write ups available from other people sitting in the front 3 rows so I will skip the fluffy stuff. The issues I still see with Cadence and EDA in general are the claims of collaboration. The stated EDA360 Alliances are:
- Star IP (ARM/MIPS/Tensillica),
- IP and Design Services,
- Foundries (TSMC, UMC, SMIC, GlobalFoundries, Common Platform, IBM),
- Hardware Dependent Software (Android, Linaro, Linux).
How exactly do you collaborate within the semiconductor design ecosystem without working with other EDA companies? I agree that EDA is built on point tools with the empty promise of unity at some point in the design process. I also know that enlightened EDA customers will never allow themselves to be locked into a single vendor solution. Cadence once had the largest and strongest partners programs (CDN Connections), which in itself could have been a platform to launch the applications business model that was referenced over and over by CDN executives.
Unfortunately, in a flat market, the Big 3 companies focus on stealing market share from each other which does not support the type of collaboration that will be required for the semiconductor design ecosystem to prosper. If the business model does not change, EDA will continue to be 3 big dogs eating at one bowl, not a pretty picture! (Joe Costello circa 1995).
47th Annual Design Automation Conference
The first Design Automation Conference I attended was in 1984, Albuquerque New Mexico, which was one of the first to allow exhibitors. It was an interesting time, so much innovation, so much excitement, the Design Automation Conference is and has always been the cornerstone of EDA. This will be my 27th DAC and certainly not my last, the parties alone are worth the trip!
This year’s DAC looks promising with Synopsys and Cadence as primary sponsors, followed by Mentor, Atrenta, Denali, Apache, Springsoft, TSMC and GlobalFoundries. This tracks with the top EDA vendor list in the DeepChip.com EDA Vendor Survey Results. The only one missing is Magma? The DAC website is new and worth checking out with 20+ new companies exhibiting this year.
The battle between TSMC and GlobalFoundires will continue at DAC. TSMC has another Ecosystem (Open Innovation Platform) booth this year with a dozen different partners displaying process qualified tools and IP. GlobalFoundries, a new addition to DAC, has 4 separate booths for partners and promotions.
Two of the partners in the TSMC Ecosystem that I have first hand experience with are Virage Logic and Solido Design. Virage has come a long way since I worked there as Director of Strategic Foundry Relationships. The transition from a boutique memory company to an industry leading IP provider is complete and now that Denali has been assimilated by Cadence I see another Virage growth spurt coming.
Solido Design has also made significant strides in adoption supported by two recent publications: Jim Hogan’s ViewPoint on Custom IC Design:
“I have always felt the job of a designer is to optimize designs within the process capabilities. The design exercise is still a process of trading off the marketing requirements of function, performance, cost and power. This is especially true in the case of custom design. There is never a perfect answer, only a most right, or said differently, the least wrong.
Designers relying on discreet manufacturing processes need to rely on accurate process models (SPICE for semiconductor). As variance increases, more models or corners are required to represent the process capability.
Variation analysis is only useful if the designer can do fast, iterative analysis, while maintaining the same accuracy. This is what “variation-aware” custom IC design is about — giving designers sufficient simulation and convergence speed to make it possible to examine design tradeoffs. In this way, instead of just doing verification, designers can proactively design-for-variation prior to tapeout without over-margining or under-designing.” Jim Hogan
Even more compelling is the Qualcomm review of the Solido tool on DeepChip “User says Solido Speeds Cadence Spectre Variation Design 5X”
I ran a 2.5 month eval of Solido Variation Designer (VD) tools for custom IC design in late 2009 and we purchased them earlier this year. Solido VD bolts onto our Cadence Virtuoso Analog Design Environment (ADE) and Spectre. Solido sped up our analysis by about 5x versus just using Cadence tools (details below). Because Solido uses Spectre’s simulation engine and full foundry models (in our case TSMC models) for its analysis, their results are identical to Spectre — with zero degradation in accuracy.
- Glenn Murphy
Qualcomm San Diego, CA
This review tracks with my Solido Taiwan experience 100%. Foundries invest significantly in their SPICE variation models. Manufacturing variation effects are documented through global and local random variation parameters, process corners and proximity effect parameters. The challenge has been how can designers efficiently use these variation models while not adding time and complexity to their project schedules. Designers need to not only analyze how the design behaves as a result of variation, but also identify design sensitivities to variation and identify how to fix the design. That is exactly what Solido Variation Designer does. Sign-up for a Solido Demo at DAC here.
Design for Manufacture @ 40nm and Below
Yielding designs at 40nm and below has redefined Design for Manufacture (DFM), the techniques implemented to modify the designs in order to make them more manufacturable, i.e., to improve functional yield, parametric yield, or reliability. Lunch (I blog for food) with my friend BP Wong, co-author of Nano-CMOS Design for Manufacturability, gave me a whole new perspective on DFM.
The DFM I unsuccessfully evangelized years ago consisted of a set of different methodologies trying to enforce some soft (recommended) design rules regarding the shapes and polygons of the physical layout of an integrated circuit. These DFM methodologies worked primarily at the full chip level. Additionally, worst-case simulations at different levels of abstraction were applied to minimize the impact of process variations on performance and other types of parametric yield loss. All these different types of worst-case simulations were essentially based on a base set of worst-case (corner) SPICE device parameter files that were intended to represent the variability of transistor performance over the full range of variation in a fabrication process.
At 40nm DFM has a new definition, driven by the pattern distortion limited yield, unpredictable silicon performance, as well as leaving much of the process entitlement behind. This results in an inferior product so many are returning to DFM to harness the full process entitlement. Classical approach through Design Rules (causing explosive design rule growth) is intractable by itself and yet cannot fully describe the parametric changes as a result of lithographical distortion as well as stress proximity differences. This stifles design productivity through excessive rule checks and yet a DRC clean design does not necessarily equate to a problem free design. Restrictive Design Rules will be used at 28nm and 20nm but at what cost?
The book suggests a bridge from physical and circuit design to fabrication processing, as well as harnessing systematic variability instead of having to apply design margins that would further reduce process entitlement available to the designers. It starts off with the discussion of the lithography related aspects of DFM. As the semiconductor industry entered the sub-wavelength domain, the traditional wisdom that chip yields are ultimately dominated by defects no longer holds. Lithography and design driven factors increasingly contribute to the final chip yield. This notion is enforced by the experience of many fabless companies whose product plans were severely delayed by manufacturing issues particularly at the beginning of a new technology node. Various fabless companies have also experienced costly mask re-spins and delays in their schedules due to printing related issues.
The book is the sequel to Nano-CMOS Circuit and Physical Design, taking design to technology nodes beyond 65nm geometries. Throughout the book, real-world examples simplify complex concepts, helping fabless designers see how they can successfully handle projects at 40nm and below. It provides a bridge that allows engineers to go from physical and circuit design to fabrication processing and, in short, make designs that are not only functional, but that also meet power and performance goals within the design schedule. It’s a good read, I highly recommend it.
Mentor Graphics Acquires 3D Field Solver (Pextra)
Mentor Graphics acquiring Pextra may not seem like big news given that EDA companies are being bought for pennies on the dollar these days, but this is VERY big news for two VERY important reasons:
- I was right
- Best EDA Acquisition of 2009
In January I commented on a fellow blogger’s post in regards to Mentor developing 3D field solver technology in-house. I suggested that Mentor would buy the technology rather than develop and named Pextra as the ideal candidate. So I was right. Being right is not a big deal in the blogosphere since I don’t trade on rumor and innuendo, but at home it is a very rare occurrence. So to my wife and children I WAS RIGHT! And when I get home I will do my “I was right dance” which closely resembles a marionette in a wind storm.
I first heard of Pextra while working with the foundries. 3D solvers are of great interest to the process people and PexRC had a documented reputation for speed and accuracy which is critical at 40nm and below. PexRC also did well in a STARC evaluation in Japan. It was refreshing to hear good things about a tool first hand from users and not marketing drones. Founded by a professor at Texas A&M and fueled by PhD students, I don’t even think Pextra had a marketing communications person. The “Speak softly and carry a big stick” ideology is a rare but effective strategy for emerging EDA companies with big stick technology. I strongly recommend it to my Strategic Foundry Relationship clients on a regular basis.
I wish I could credit my superior psychic investigative skills but I first confirmed the acquisition on LinkedIn. After meeting Peter Weiping Shi we linked and when his job status changed I was notified. Social Media win! A much stronger second clue was Peter at ISQED last week with a Mentor Badge. And the final and most compelling clue was the Pextra website (www.pextracorp.com) being diverted to Mentor.
Hopefully once Daniel Payne reads this blog he can talk in more depth about the technology as he is famous for his technical reviews. Mentor is probably holding the announcement for the Design Automation Conference in June or the press release is in the Mentor corporate signature quagmire. Either way I hope this blog speeds the introduction and gets the Pextra people and the PexRC technology the respect that is due. Enjoy the earnout fellas, you deserve that and more!
China Semiconductor Bubble
The China Bubble is coming (followed by the Obama Bubble in 2012) and no surprise, there is a website dedicated to just that: ChinaBubbleWatch. This is not my field of expertise but my friends in China are quite concerned, the semiconductor industry should be concerned as well. Correct me if I’m wrong but a Chinese version of the 2009 U.S. bubble would be a serious pothole on the road to semiconductor riches.
The Chinese government led economy is the envy of the world growing at an estimated 8% annually, even while the world economy contracted 2%+ in 2009. Estimated is the best you will get since censorship in China is an Olympic event. About a decade ago the Chinese authoritarian regime adopted a “growth at all costs” philosophy that continues to mystify the world markets and defy the laws of economics. John Maynard Keynes would be dumbfounded!
DanielNenni 64 Chinese billionaires on Forbes list http://tinyurl.com/yj4wcqt More than doubled! A China bubble is coming!
Even during the 2009 world wide financial crisis the China economy grew 8%. Growth at all costs. In 2009 the Chinese government pumped close to $600B of stimulus into the economy. In comparison to the U.S. stimulus, factoring in the GDPs, using D.A.N. math, China roughly outspent Obama 3:1. Of course that doesn’t count the latest Obama health care stimulus plan that was just passed.
Forbes did an interesting article on the China Bubble comparing it to a Ponzi Scheme headed by the China Central Bank, the people who print the money. Per Forbes:
The U.S. government’s $7.2 trillion in debt at the end of June represented 50% of gross domestic product. The Chinese government’s officially disclosed $840 billion in public debt represents less than 20% of GDP. But the People’s Bank of China and the treasury are also on the hook for potentially $1.5 trillion in off-balance-sheet debt owed by cities and provinces and entities they control. They’re also implicitly obliged to backstop $1 trillion, both in loans that “policy banks” were directed to issue, even when they made no economic sense, and nonperforming loans that the government removed from the books of state-owned commercial banks over the past decade.
Add it up and the national government is responsible for debt equal to over 70% of 2009 GDP. That doesn’t count any loans generated this year that might go sour amid a 30% increase in debt balances nationwide. (The U.S. government, in addition to its direct debt equal to 50% of GDP, is responsible for cosigning of mortgage borrowers’ obligations equal to another 18% of GDP.)
Again, not my area of expertise, but I am a property owner, or slum lord as my renters affectionately call me, and I know a housing meltdown when I see one. My friends in China mention vacant buildings and empty housing projects everywhere. China built the world’s largest mall in 2005, today it is 99% empty.
Back to semiconductors. As I mentioned in a previous blog, TSMC Yields Recovery, TSMC is my economic bellweather. Semiconductors are where electronics begin and the sales of electronic devices is where economic growth begins. I predicted a strong “V” recovery and that is pretty much what we have seen. I now amend that prediction to an upper case “V” followed by a lower case “v” fueled by a China bubble. For more information on what actually caused the U.S. bubble read my award winning blog: Colossal Failure of Common Sense.
Semiconductor Enabled Mobile Internet
The mobile internet market will be the single biggest semiconductor innovation driver in the coming decade. The technology required to continually integrate electronic devices into a single handset is daunting. The amounts of information that will need to be retrieved, processed, stored, and displayed will be catastrophic. Reference the Morgan Stanley Mobile Internet Report.
I touched on this subject in my blog Semiconductor IP Innovation and the mention of the Mobile Industry Processor Interface or MIPI as it is affectionately referred to. The semiconductor industry has done a decent job with industry standards which allow consumers like myself a choice of vendors for leading edge mobile technologies.
Next month brings the premier exhibition for mobile internet devices. The Mobile World Congress is the combination of the world’s largest exhibition for the mobile industry and a congress featuring prominent Chief Executives representing mobile operators, vendors and content owners from across the world. CEO Keynote Speakers this year include one of my favorites Eric Schmidt of Google. The CEOs this year will offer their views of the new mobile landscape, sharing perspectives and insights that serve to strengthen and advance the industry. This conference was first held in 1987 and attracts 50,000+ attendees. Follow me to Barcelona Spain via Twitter: DanielNenni
Semiconductor design enablement is represented at the Mobile World Congress by the top IP companies ARM, Virage Logic and MIPS. Even an EDA company (Mentor Graphics) is exhibiting this year. The MIPI Alliance Zone will be in Hall 2 (2H41) with Silicon Valley companies leading the way. At the physical interface layer there is Mixel, the leader in SERDES/PHY MIPI technology. At the controller level there is Virage Logic and Arasan. Virage licensed the MIPI controller from the AMD-ATI group last year and markets complete IP solutions that include embedded processors (ARC), embedded memories, and interface IP. Arasan “The Bus Stops Here” provides MIPI, I/O, and storage IP.
Currently the MIPI standard uses D-PHY technology with communication speeds of 500M-1GBits. The D comes from the Roman numeral 500. The latest draft of the MIPI standard uses M-PHY technology with communication speeds of 1000M-5GBits. The M comes from the Roman numeral 1000. In addition to higher speeds, the M-PHY will also consume less and dissipate less power. Mixel and Arasan are both contributing MIPI members and have M-PHY development activity on their respective websites. More detailed information is available on the Mixel M-PHY web page.
The ultimate gadget exhibition is next week in Las Vegas. The International Consumer Electronics Show starts on January 7th and boasts 2,500 exhibitors with an estimated 20k+ new products for you to see. MIPI will be well represented with the new Netbooks and Tablet PCs. Microsoft’s Steve Ballmer will keynote followed by CEOs from Ford, Intel, Qualcomm, and Nokia. The most memorable CES show for me was when Bill Gates argued that hardware will always limit computer innovation. Andy Grove followed with an argument for software being the limiting factor. As it turns out both are true.
2010 Semiconductor Forecast
While the worst is definitely over, 2009 will probably be known as one of the steepest revenue declines in semiconductor history due to a drop in orders. The official semiconductor recession however started with the Q4 2008 financial reports, but could be seen even earlier in the year with failing forecasts and bugling inventories. So realistically it was the semiconductor debacle of 2008/09.
Looking forward, Q1 is historically weak for semiconductors but based on what I see with the foundries and their top customers business will be brisk. In fact, Q1 2010 may be one of the best revenue Q1s for the semiconductor sector in a long time.
Semiconductor distributors Arrow Electronics and Avnet have both told analysts that demand in North America is increasing with accelerated growth in Q1. Arrow Electronics serves as a channel partner for approximately 800 suppliers and 130,000 customers through more than 340 locations in 53 countries. Avnet operates in more than 70 countries, distributing electronic components from leading manufacturers to more than 100,000 customers around the world.
DRAM supply was already lagging demand when Windows 7 came out and put even more pressure on PC and laptop users to upgrade. Micron Technology, the DRAM bellwether, is now profitable for the first time in three years. Expect increased pricing, long lead times, and continued DRAM allocation in 2010.
FPGA companies Xilinx and Altera both bumped up sales guidance this quarter. Xilinx announced December quarter sales are expected to be up approximately 16% to 20% sequentially. This is a revision from previous sales guidance of up approximately 6% to 10% sequentially. Gross margin is expected to be approximately 64%, up from prior guidance of approximately 62% to 63%. Altera now expects sales for the fourth quarter to be 15 percent to 18 percent above third quarter levels. Previous guidance was for sales growth of 6 percent to 10 percent.
Semiconductor giants Qualcomm and Broadcom both projected optimism for the coming year. Qualcomm is hoping for a 10% increase in quarter over quarter revenues while Broadcom raised sales guidance for the current quarter. Broadcom revenue is estimated to increase sequentially from the third quarter of 2009 by roughly 5% to approximately $1.32 billion, compared to prior guidance of $1.25 billion.
In 2010 you will see the semiconductor industry back on track with revenue and shipments substantially greater than 2009. As mentioned in Semiconductor Industry 2008-2018, the mobile internet market will drive semiconductors for the next decade with an incredible integration of electronic devices targeting the 6,792,600,000 consumers on the earth today. The big question is will the foundries be able to satisfy the ever increasing fabless semiconductor demand in the coming decade?
As I mentioned in Black Friday and the Predicted Semiconductor Shortages , a strong indicator of future semiconductor growth is foundry capital expenditure plans. TSMC, the #1 foundry provider, spent more than $3B on manufacturing equipment this year. UMC and Chartered Semi were at $500M, and SMIC a mere $190M. Clearly TSMC sees future capacity issues where the other foundries do not. As TSMC’s capital expenditures rival semiconductor titans Intel and Samsung, what does TSMC know that the other foundry providers don’t? Unfortunately once they find out it will probably be too late, allocation will be the new semiconductor norm.
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